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    • 专利摘要:
    The present description relates to a memory circuit (200) comprising: - a plurality of elementary storage cells (10) arranged in a matrix according to rows and columns, the cells of a same column sharing a same read bit line (RBL ) and a same write bit line (WBL); - an internal control circuit (CTRL) suitable for implementing a calculation operation comprising the simultaneous activation in read mode of at least two rows of the matrix; and - a permutation circuit (30) comprising a data input register (32), a configuration register (36), and an output port (34), the permutation circuit (30) being adapted to supply on its output port (34) the data stored in its input register (32) permuted according to a permutation defined according to the state of its configuration register (36).
    公开号:FR3088767A1
    申请号:FR1871578
    申请日:2018-11-16
    公开日:2020-05-22
    发明作者:Henri-Pierre CHARLES；Maha Kooli；Jean-Philippe Noel
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    TITLE: Memory circuit adapted to implement calculation operations
    Technical Field This description relates to the field of memory circuits. It relates more particularly to a memory circuit suitable for implementing calculation operations.
    Prior art [0002] 11 has already been proposed, in the European patent application ΞΡ3252774 (DD16812 / B14843), in the French patent application N ° 17/62534 (DD17938 / B16054) filed on December 19, 2017, in the application for French patent N ° 17/62470 (DD17955 / B16064) filed on December 19, 2017, in French patent application N ° 17/63221 (DD17956 / B16065) filed on December 26, 2017, and in French patent application N c 17 / 62468 (DD17885 / B16288) filed on December 19, 2017, a memory circuit suitable not only for storing data, but also for performing, in situ, when accessing the content of the memory, a certain number of logical operations and / or arithmetic whose operands are data stored in the memory. This circuit comprises, as in a conventional memory circuit, a plurality of elementary cells arranged in a matrix according to rows and columns, and a control circuit adapted to implement operations for reading or writing data in rows of the matrix. Unlike a conventional memory circuit in which only one row of the matrix can be selected at a time during a read operation, the control circuit is adapted to simultaneously select in read a plurality of rows of the matrix so as to perform an operation having as operands data contained in the selected rows.
    B17236 - DD18432 [0003] It would be desirable to at least partially improve certain aspects of such a memory circuit.
    Summary of 1 1 invention [0004] Thus, an embodiment provides a memory circuit comprising:
    - A plurality of elementary storage cells arranged in a matrix according to rows and columns, the cells of the same column sharing the same read bit line and the same write bit line;
    an internal control circuit suitable for implementing a calculation operation comprising the simultaneous activation in reading of at least two rows of the matrix; and
    a permutation circuit comprising a data input register, a configuration register, and an output port, the permutation circuit being adapted to supply on its output port the data stored in its input register permuted according to a permutation defined according to the state of its configuration register.
    According to one embodiment, the internal control circuit is adapted to implement a permutation operation comprising:
    - the activation in reading of at least a first row of the matrix;
    - copying data read from the read bit lines of the matrix into the data input register of the permutation circuit;
    ~ the copy of data supplied on the output port of the permutation circuit on the write bit lines of the matrix; and
    activating in writing at least one row of the matrix [0006] According to one embodiment, the permutation operation further comprises:
    - the activation in reading of at least a second row of
    B17236 - DD18432 copying of data read from the read bit lines of the matrix in the configuration register of the permutation circuit.
    the matrix ; and [0007] According to one embodiment, the memory circuit comprises, in addition to the matrix of elementary storage cells, an additional memory intended for storing configuration data of the permutation circuit.
    According to one embodiment, the permutation operation further comprises copying data read from the additional memory in the configuration register of the permutation circuit.
    According to one embodiment, the additional memory is a non-volatile memory.
    According to one embodiment, the permutation circuit comprises a plurality of elementary permutation cells each comprising two data inputs el and e2, two data outputs si and s2, and a configuration input c.
    According to one embodiment, the permutation circuit comprises * (2 * log2 (K) -1) elementary permutation cells arranged according to a Benes network, where K is an integer designating the dimension of the input register and the output port of the permutation circuit.
    According to one embodiment, the permutation circuit comprises 16 elementary permutation cells arranged in 5 rows, the rows of row 1 = 1 to 1 = 3 each comprising 4 elementary cells, and the rows of row 1 = 4 to 1 = 5 each comprising 2 elementary cells, the input register and the output port of the permutation circuit being of dimension 8, and 1 being an integer ranging from 1 to 5.
    B17236 - DD18432 According to one embodiment, the memory circuit further comprises an configurable input-output circuit for connecting the read bit lines of the matrix to the input register of the permutation circuit and / or for connect the write bit lines of the matrix to the output port of the permutation circuit.
    [0014]
    According to one embodiment, further comprises a calculation circuit adapted to implement logical or arithmetic operations having as operands data stored in the matrix of elementary storage cells of the memory circuit.
    According to one embodiment, the output circuit is further configurable to connect the read bit lines of the matrix to an input register of the calculation circuit and / or to connect the bit lines of write the matrix to an output port of the calculation circuit.
    BRIEF DESCRIPTION OF THE DRAWINGS These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:
    [Fig. 1] FIG. 1 schematically represents an example of a memory circuit suitable for implementing calculation operations;
    [Fig. 2] Figure 2 is a more detailed electrical diagram of an example of an elementary cell for storing a circuit, memory;
    [Fig. 3] Figure 3 schematically shows an example of a memory circuit according to one embodiment;
    [Fig. 4] Figure 4 shows in more detail an embodiment of a permutation circuit of the memory circuit of Figure 3;
    B17236 - DD18432 [Fig · 5] Figure 5 shows an embodiment of an elementary permutation cell of the permutation circuit of Figure 4;
    [Fig- 6] Figure 6 shows another embodiment of a permutation circuit of the memory circuit of Figure 3;
    [Fig. 7] Figure 7 schematically shows another embodiment of a memory circuit according to one embodiment;
    [Fig. 8] Figure 8 shows in more detail an embodiment of the memory circuit of Figure 7;
    [Fig. 9] FIG. 9 schematically represents an example of a data processing method which can be implemented by a memory circuit according to one embodiment;
    [Fig. 10] FIG. 10 schematically represents another example of a data processing method which can be implemented by a memory circuit according to one embodiment; and [Fig. 27] 11] FIG. 11 schematically illustrates another example of a data processing method which can be implemented by a memory circuit according to an embodiment.
    Description of the embodiments The same elements have. have been designated by the same references in the various figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and. may have identical structural, dimensional and material properties.
    B17236 - DD18432 For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular the complete realization of a circuit, memory adapted to implement calculation operations by simultaneous activation in reading of a plurality of rows of an array of elementary cells has not been detailed, the embodiments described being compatible with the known architectures of such circuits, and in particular those described in the aforementioned patent applications.
    Unless otherwise specified, when reference is made to two elements connected together, this directly means
    connected without elements i n t ermediate to other than of conductors, and .1 when 1 'we are referring to two elements linked or coupled s enters them it means that these of them
    elements can be connected or be linked or coupled via one or more other elements.
    Unless otherwise specified, the expressions approximately, approximately, substantially, and of the order of mean to the nearest 10%, preferably to the nearest 5%.
    In the following description, the references to high and low level signals must be interpreted relatively, as corresponding to two distinct states of the binary signals processed by the circuits described. By way of example, the high level of the signals corresponds to potentials of the order of a high supply potential VDD of the circuits described (for example equal to VDD to within 0.5 V), and the low level of signals correspond to potentials on the order of a low supply potential GND of the circuits described (for example equal to GND to the nearest 0.5 V).
    Figure 1 shows schematically an example of a memory circuit 100. All the elements of the circuit
    B17236 - DD18432 memory 100 is for example integrated in and on the same integrated circuit chip.
    The memory circuit 100 of Figure 1 comprises a plurality of elementary cells 10 arranged in a matrix according to rows and columns. In the example of FIG. 1, the matrix comprises M rows and N columns, where M and N are integers greater than or equal to 2.
    Each elementary cell 10 is adapted to store a data bit. The elementary cells 10 of the same column of the matrix are connected to the same conductive data output track or RBL read bit line of the circuit, and to the same conductive data input track or bit line WBL write of the circuit, it being understood that the elementary cells 10 of separate columns are connected to separate RBL read bit lines and to separate WBL write bit lines. In other words, for each column of rank j of the matrix, where j is an integer ranging from 0 to Nl, the memory circuit 100 comprises a read bit line RBL <j> and a write bit line WBL <j > specific to the column, connecting the cells of the column to each other. The bit lines for reading RBL <j> and writing WBL <j> extend in the direction of the columns of the matrix, that is to say vertically in the orientation of FIG. 1. The lines of read bit RBL <j> and write WBL <j> are connected to the same input-output circuit 10 of the memory circuit, for example arranged at one end of the columns of the matrix.
    The memory circuit 100 further comprises a row selection circuit RS, for example arranged at one end of the rows of the matrix.
    The memory circuit 100 further comprises a control circuit CTRL adapted to receive instructions from a device external to the memory circuit, and to order in
    B17236 - DD18432 consequently the elementary cells 10 of the memory circuit via the row selection circuit RS and / or via the 1 input-output circuit 10.
    In this example, the memory circuit is suitable not only for storing data, but also for performing, insitu, when accessing the content of the memory, a certain number of logical and / or arithmetic operations having as operands data stored in the memory circuit. The results of the calculations can be transmitted to circuits external to the memory circuit, and / or be rewritten in the memory circuit without passing through circuits external to the memory circuit, and in particular by a data bus external to the memory circuit.
    In the example of Figure 1, the memory circuit 100 includes a calculation circuit 20, for example disposed at one end of the columns of the matrix, adapted to implement logical or arithmetic operations having data operands stored in the storage matrix of the circuit, memory. In the example shown, the calculation circuit 20 comprises a data input register 22, for example of dimension N, and a data output port 24, for example similarly, dimension N. The input register of data 22 and the data output port 24 of the calculation circuit 20 are connected to the input-output circuit 10 of the memory circuit. To implement a calculation operation by means of circuit 20, the control circuit CTRL commands the reading of one or more operand data in the storage matrix of the memory circuit and the writing of these operand data, via circuit d input-output 10, in the data input register 22 of the calculation circuit 20. The control circuit CTRL further controls the circuit. 2 0 to carry out the desired operation. The result of the operation is supplied on the output port 24 of the calculation circuit 20, and
    B17236 - DD18432 can be directly rewritten in the storage matrix of the memory circuit via the output input circuit 10, without passing through circuits external to the memory circuit.
    Figure 2 is a detailed electrical diagram of an example of an elementary cell 10 of a memory circuit of the
    type of: written in relationship with the trust swear 1.[0041] The celi elementary 10 of the figure 2 is a cell to ten transistors. El 1 st includes a cell
    SRAM 12 storage with six transistors, and two RPT and RPF read ports with two transistors each. The storage cell 12 comprises two inverters (two transistors each) mounted in antiparallel between a first BLTI node for storing a data bit, and a second BLFI node for storing a data bit complementary to the bit stored on the node BLTI. The storage cell 12 further comprises a first access transistor Tl, connecting, by its conduction nodes, the node BLTI to a conductive track WBLT called write bit line, and a second access transistor T2, connecting , by its conduction nodes, the node BLFI has a conductive track WBLF called the complementary write bit line. The gates of the transistors Tl and T2 are connected to the same conductive write control track WWL. The RPT read port includes two transistors T3 and T4 connected in series, via their conduction nodes, between a conductive track VGNDT for applying a reference potential and. a conductive RBLT output track called read bit line. The transistor T3 is located on the track side VGNDT and has its gate connected to the node BLTI, and the transistor T4 is located on the track side RBLT and has its gate connected to. a conductive RWLT read control track. The RPF read port includes two transistors T5 and. T6 connected in series, via their conduction nodes, between a conductive track VGNDF
    B17236 - DD18432 of application of a reference potential and a conductive track of RBLF output called bit line of complementary reading. The transistor T5 is located on the track side VGNDF and has its gate connected to the node BLF1, and the transistor T6 is located on the track side RBLF and has its gate connected to a track
    conductor of control of reading RWLF. In this example, transistors Tl, T2, T3, T4, T5, T6 are transistors N channel MOSIn a circuit memory of type described in relationship
    with FIG. 1, the elementary cells of the same row of the circuit are interconnected via their conductive tracks WWL, respectively RWLF, respectively RWLT, and the elementary cells of the same column of the circuit are interconnected via their conductive tracks RBLT, respectively VGNDT , respectively WBLT, respectively
    WBLF, respectively VGNDF, respectively RBLF. In other words, the cells of the same row share the same conductive track WWL, the same conductive track RWLF, and the same, conductive track RWLT, and the cells of the same column share the same conductive track RBLT, a same conductor track VGNDT, same conductor track WBLT, same conductor track WBLF, same conductor track VGNDF, and same conductor track RBLF. The cells of distinct rows have conductive tracks WWL, respectively RWLF, respectively RWLT, distinct, and the cells of distinct columns have conductive tracks RBLT, respectively VGNDT, respectively WBLT, respectively WBLF, respectively VGNDF, respectively RBLF, distinct . For example, the conductive tracks WWL, RWLF and RWLT are connected to the row selection circuit RS of the memory circuit, and the conductive tracks RBLT, VGNDT, WBLT, WBLF, VGNDF and RBLF are connected to the input circuit- output 10 of the memory circuit.
    B17236 - DD18432 By way of example, the RBLT read bit line and the WBLT write bit line of cell 10 in FIG. 2 correspond respectively to an RBL read bit line and to a line WBL write bit of the memory circuit of FIG. 1. For the sake of simplification, in the memory circuit figures of the present application (FIGS. 1, 3 and 7), a single line of read bit and a single line of write bits have been represented per elementary cell of the memory circuit. In practice, the embodiments described can be implemented either in memory circuits consisting of elementary cells with a single read bit line and a single write bit line, or in memory circuits consisting of elementary cells with two complementary read bit lines, for example of the type described in relation to FIG. 2.
    To perform a reading of an elementary cell of the type described in relation to FIG. 2 via its reading port RPT, the reading bit line RBLT of the cell is first preloaded at a high level, for example at the supply voltage VDD of the memory circuit. The conductive track VGNDT is itself kept at a low level, for example at the low potential GND with respect to which the supply voltage VDD of the memory circuit is referenced.
    The transistor T4 of the cell is then turned on by applying a high level signal to the conductive track RWLT of the cell. After the activation of the transistor T4, the conductive track RBLT discharges if the potential of the node BLTI is at a high level (transistor T3 on), and remains substantially at its precharge level if the potential BLTI is at a low level (transistor T3 blocked).
    Reading the potential of the RBLT track via the input-output circuit 10 of the memory circuit makes it possible to determine the value of the data bit stored in the elementary cell.
    B17236 - DD18432
    The cell can also be read in substantially the same way via its RPF read port, To implement calculation operations, in a memory circuit made up of elementary cells 10 of the type described in relation to FIG. 2, the control circuit CTRL of the memory circuit is adapted to activate simultaneously in reading (via the row selection circuit RS) two, or a number greater than two, of elementary cells of the same column of the memory circuit, via the ports d 'RPT access, and / or via the RPF access ports of these cells.
    As an illustrative example, it is considered that two elementary cells 10 of the same, column are activated simultaneously in reading via their RPT and ports. RPF. To do this, after having preloaded the RBLT and RBLF read bit lines of the column to a high level and set the reference conductive tracks VGNDT and VGNDF of the column to a low level, the selection transistors T4 and T6 of the two
    cells selected are simultaneously turned on, via
    the conducting tracks RWLT and RWLF of the rows
    correspo. ridiculous. We denote by A and B respectively the values binaries stored on the BLTI nodes of the two cells considered. Complementary binary values NA
    and NB are then stored on the respective BLF1 nodes of the two cells. The conductive track RBLT output of the column remains at its high precharge level only if the two values A and B are at a low level. Thus, the level read on the RBLT output track of the column at the end of
    1 1 operat: reading ion corresponds to the result NA.NB of a ioi operat n OR NOT logical calculation between the two, cells memory £ selected. In addition, the output conductive track RB LL · ' 1 of the column remains at its high preload level
    only if the two values A and B are at a high level.
    B17236 - DD18432
    Thus, the level read on the RBLF output track of the column at the end of the read operation corresponds to the result A.B of a logical calculation operation AND between the two selected memory cells.
    By simultaneously activating in reading a number greater than two of cells of the same column, the above-mentioned calculation operations can be implemented with a number of operands greater than 2. In addition, by activating simultaneously in reading several columns of the memory circuit, these calculation operations can be implemented on words of several bits.
    Thus, basic logic calculation operations can be implemented directly in the memory, without having to pass the data through an arithmetic and logic unit external to the circuit.
    To allow rewriting of the result. a calculation operation without passing the calculated data by circuits external to the memory circuit, and in particular by a data bus external to the memory circuit, the input-output circuit 10 of the memory circuit can comprise an internal redirection circuit (not detailed) making it possible to connect the read bit line or lines of each column of the memory circuit to a data entry node of the column and / or of another column of the matrix, pax 'example to the track conductive WBLT and / or to the conductive track WBLF of the column or of another column of the matrix in an architecture of the type described in relation to FIG. 2.
    To implement more complex calculation operations, for example arithmetic operations, the operand data can be transmitted to the calculation circuit
    20. For this, the internal redirection circuit of the input-output circuit 10 can be configured to connect the read bit lines of the circuit.
    memory to input nodes of the
    B17236 - DD18432 data input register 22 of the calculation circuit 20. Once the operation has been carried out, the internal redirection circuit of the 1 input-output circuit 10 can be configured to connect the write bit lines of the circuit memory at output nodes of the data output port 24 of the calculation circuit 20 so as to allow the rewriting of the result of the calculation operation without passing the calculated data through circuits external to the memory circuit, and in particular by a data bus external to the memory circuit.
    Figure 3 schematically shows an example of a memory circuit 200 according to one embodiment. As in the example in FIG. 1, all of the elements of the memory circuit 2 00 can be integrated in and on the same semiconductor chip.
    The memory circuit 200 of Figure 3 comprises the same elements as the memory circuit 100 of Figure 1, arranged in substantially the same manner.
    The memory circuit 200 further comprises a permutation circuit 30. The permutation circuit 30 comprises a data input register 32 of dimension K, that is to say adapted to receive simultaneously (in parallel) and to memorize K data bits, and a data output port 34 of the same dimension K, that is to say adapted to supply simultaneously (in parallel) K data bits. By way of example, the dimension K of the permutation circuit 30 is equal to the number N of columns of the array of storage cells of the memory circuit. The permutation circuit 30 further comprises a configuration register 36. The permutation circuit is adapted to supply on its output port the K bits stored in its data input register, permuted according to a permutation defined as a function of the state of its configuration register 36.
    B17236 - DD18432 By permutation, we mean here that the K input bits of the circuit 30 are copied at the output of the circuit 30, but in a different order. The total number of permutations possible for an input vector of K bits is equal to K! (K factorial), that is K * (K-l) * (K-2) * ... * 2 * 1. The permutation circuit 30 is for example configurable, via its configuration register 36, to implement any of the K! possible permutations.
    The data input register 32, the data output port 34 and the configuration register 36 of the permutation circuit 30 are connected to the 1 input-output circuit 10 of the memory circuit. To implement a permutation operation by means of circuit 30, the control circuit CTRL commands the reading of an input data item in the storage matrix of the memory circuit, the writing of this data item, via the input-output 10, in the data input register 32 of the permutation circuit 30, the reading of configuration data in the storage matrix of the memory circuit, and the writing of this data, via the input-output 10, in the configuration register 36 of the permutation circuit 30. For this, the internal redirection circuit of the input-output circuit 10 can be configured to connect the read bit lines of the memory circuit to nodes d input of the data input register 32 of the permutation circuit 30 and / or of input nodes of the configuration register 36 of the permutation circuit 30. The result of the permutation is supplied on the output port 34 of the circuit 30, and can be rewritten directly, in the storage array of the memory circuit via the input-output circuit 10, without passing through circuits external to the memory circuit. For this, the internal redirection circuit of the input-output circuit 10 can be configured to connect the write bit lines of the memory circuit.
    B17236 - DD18432 to output nodes of the data output port 34 of the permutation circuit 30.
    Figure 4 shows in more detail an embodiment of the permutation circuit 30 of the memory circuit of Figure 3. In this example, we consider, by way of illustrative example, a permutation circuit of dimension K = 8 , that is to say in which the input 32 and output 34 registers are each of dimension K = 8. Those skilled in the art will be able to generalize this example to the realization of a dimension permutation circuit Any K, where K = 2 H (two powers H) and H is a positive integer. Note that in
    the case where the dimension D of the data of memory is not not a well session two, we can choose sir K greater than D, by example equal at the first power of two superior to D (K =: 2 H with H such that 2 Η_1 <D <K 2 H ), and complete the
    memory data by 0 to obtain input words of dimension K.
    In the example of FIG. 4, the permutation circuit is produced by means of a Benes network consisting of (K / 2) * (2 * log2 (K) -1) elementary permutation cells 40. In the example of FIG. 4, the elementary permutation cells 40 are arranged in a matrix according to 2 * log2 (K) -l rows and K / 2 columns.
    Each elementary permutation cell 40 comprises two input nodes el and e2, two output nodes si and s2, and a configuration node c. Each elementary cell 40 is suitable for copying on its output nodes si and s2 the signals applied respectively to its input nodes el and e2, or for copying on its output nodes si and s2 the signals applied respectively to its nodes input e2 and el, depending on the state of the signal applied to its confiauration node
    B17236 - DD18432 The K input nodes el, e2 of the cells 40 of the row of rank 1 = 1, with 1 integer ranging from 1 to 2 * loga (K) -1, are connected, preferably connected, respectively to. K storage nodes of the data input register 32 of the permutation circuit. The K output nodes si, s2 of the cells 40 of the row of row l = 2 * log2 (K) -1 are connected, preferably connected, respectively to the K. output nodes of the output port 34 of the permutation circuit. In this example, the configuration register 36 includes (K / 2) * (2 * log2 (K) -1) storage nodes connected respectively to the configuration nodes c of (K / 2) * (2 * log2 (K) -1) cells 40 of the permutation circuit.
    In each row of row 1 = 1 to l = log2 (K) -1, the cells of the row are distributed in groups of n = 2 1 neighboring cells whose output nodes if, s2 are connected to the nodes input el, e2 of the cells of the next row (the row of row 1 + 1) according to a cross connection defined as follows:
    - each of the first n / 2 cells of the group has its output node if connected, preferably connected, to the node el of the cell of the same position in row 1 + 1;
    each of the last n / 2 cells of the group has its output node s2 connected, preferably connected, to the node. e2 of the cell of the same position in row 1 + 1;
    - each of the first n / 2 cells of the group has its node
    exit s 2 connected, from preference connected to el knot of the cell of position m + 2 1 ' 1 in row 1 + 1 (with M whole going of 1 to K / 2 designating the position from the c : ellule
    considered in row of row 1); and each of the last n / 2 cells of the group has its output node if connected, preferably connected, to the node. e2 of position cell m-2 1 ' 1 in row 1 + 1.
    B17236 - DD18432 The network is symmetrical with respect to the central row of row l = log2 (K), that is to say that, in each row of row l = log2 (K) at l = 2 * log2 (K) -2, the cells of the row are distributed by groups of n == 2 (2 * iog 2 (k) -ii) neighboring cells whose output nodes if, s2 are connected to the input nodes el , e2 of the cells of the next row (the row (1 + 1) according to a cross link defined as follows:
    - each of the first n / 2 cells of the group has its output node if connected, preferably connected, to the node el of the cell of the same position in row 1 + 1;
    - each of the last n / 2 cells of the group has its output node s2 connected, preferably connected, to node e.2 of the cell of the same position in the row 1 + 1;
    each of the first n / 2 cells of the group has its output node s2 connected, preferably connected, to the node el of the position cell m + 2 i2 * lo 92 (K! ' 2 '1; in row 1 + 1 ; and
    - each of the last n / 2 cells of the group has its output node if connected, preferably connected, to node e2 of the position cell m-2 (2 * iog 2 ικ) -2-1) in years j_ has row 1 + 1.
    FIG. 5 represents an example of an elementary permutation cell 40 of the permutation circuit of FIG. 4.
    The cell 40 of Figure 5 comprises two multiplexers muxl and mux2, for example identical, of two inputs to an output. Each of the multiplexers muxl and mux2 includes two input nodes a1 and a2, an output node b1, and. a configuration node cl, and is adapted to supply on its output node bl one or the other of the signals applied to its input nodes a1 and a2, depending on the state of the signal applied to its node configuration cl.
    The input node el of the cell 40 is connected to the input node al of the muxl multiplexer and to the input node a2 of the mux2 multiplexer. The input node e2 of the cell
    B17236 - DD18432 is connected to the input node a2 of the muxl multiplexer and to the input node al of the mux2 multiplexer. The configuration node c of cell 40 is. connected to the configuration nodes cl of the muxl and mux2 multiplexers.
    Depending on the state of the signal applied to its configuration node c, the cell 40 provides on its node if the signal applied to its node el and provides on its node s2 the signal applied to its node e2, or provides on its node if the signal applied to its node e2 and provides on its node s2 the signal applied to its node el.
    FIG. 6 shows another example of an embodiment of the permutation circuit 30 of the memory circuit of FIG. 3. As in the example in Figure 4, we consider here, at. As an illustrative example, a permutation circuit of dimension K = 8, that is to say in which the input registers 32 and output 34 are each of dimension K = 8.
    In the example of Figure 6, the circuit. permutation consists of a network of 16 elementary permutation cells 40, for example identical or similar to those of the permutation circuit of FIG. 4.
    In the example of FIG. 6, the elementary permutation cells 4 0 are, arranged in 5 rows, the rows of row 1 = 1 to 1 = 3 each comprising 4 elementary cells 40, and the rows of row 1 = 4 to 1 = 5 each comprising 2 elementary cells 40.
    The K input nodes el, e2 of the cells 40 of the row of row 1 = 1 are connected, preferably connected, respectively, to the K storage nodes of the data input register 32 of the permutation circuit. In this example, the configuration register 36 comprises 16 storage nodes connected respectively to the configuration nodes c of the 16 cells 40 of the permutation circuit.
    B17236 - DD18432 As in the example in FIG. 4, in each row of row 1 = 1 to 1 = 2, the cells of the row are distributed in groups of 11 = 2 1 neighboring cells including the output nodes if, s2 are connected to the input nodes el, e2 of the cells of the next row (the row of row 1 + 1) according to a cross connection defined as follows:
    - each of the first n / 2 cells of the group has its output node if connected, preferably connected, to the node el of the cell of the same position in row 1 + 1;
    - each of the last n / 2 cells of the group has its output node s2 connected, preferably connected, to the node e2 of the cell of the same position in the row 1 + 1;
    ~ each of the first n / 2 cells of the group has its output node s2 connected, preferably connected, to the node el of the position cell m + 2 1 ' 1 in the row .1 + 1; and
    - each of the last n / 2 cells of the group has its output node if connected, preferably connected, to node e2 of the position cell m-2 1 ' 1 in row 1 + 1.
    Unlike the example in FIG. 4, the network in FIG. 6 is not symmetrical with respect to the central row of rank l = log2 (K) = 3. In the example of FIG. 6, the first cell of the row of row 1 = 4 has its node el connected, preferably connected, to the node s2 of the first cell of the row of row 1 = 3, and its node e2 connected, preferably connected, to the node if of the second cell of the row of row 1 = 3. The second cell in the row
    1 = 4 has its node el connected, preferably connected, to node s2 of the third cell of the row of row 1 = 3, and its node e2 connects, preferably connected, to the node si of the fourth cell of the row of rank 1 = 3. The first cell of the row of row 1 = 5 has its node el connected, preferably connected, to the node si of the third cell of the row of row 1 = 3, and its node e2 connected, preferably connected, to the node si of the second cell of the row of row 1 = 4. The
    B17236 - DD18432 second cell of row of row 1 = 5 has its node el connected, preferably connected, to node s2 of first cell of row of row 1 = 4, and its node e2 connected, preferably connected, to node s2 of the second cell of the row of row 1 = 3. The 8 output nodes of the output port 34 of the permutation circuit are connected, preferably connected,
    re specti.vem.ent at the node if d and there first cell of the row of rank 1 = 3, at node at; 1S- 'JL of the first cell of the row of rank 1 = 4, at node if of the first cell of the row of rank 1 = 5, at node s2 of the first cell of the row of rank 1 = 5, at node if of the two i th cell of the row of rank 1 = 5, at node s2 of the second cell of the row. of rank 1 = 5, at node s2 of the second cell of the row of rank 1 = 4, and at node s2 of quat irième celli Isle ae 1 a ra: born of rank 1 = 3.
    An advantage of the permutation circuit of FIG. 6 is that it comprises a number of elementary permutation cells 40 which is less than that of FIG. 4. This makes it possible to reduce 11 congestion and the electrical consumption of the circuit, while allowing to implement all the K! possible permutations for an input vector of dimension K. In addition, this makes it possible to reduce the dimension of the configuration register 36 of the permutation circuit.
    More generally, other arrangements of permutation circuits can be provided, using a number of elementary cells which can range from logsiKl + 1) to (K / 2) * (2 * log2 (K) -1).
    [0073]
    FIG. 7 schematically represents another example of a memory circuit 300 according to one embodiment.
    As in the example in FIG. 3, all of the elements of the memory circuit 300 can be integrated in and on the same semi-inverting chip.
    B17236 - DD18432 The memory circuit 300 of FIG. 7 differs from the memory circuit 200 of FIG. 3 mainly in that it comprises, in addition to the main memory formed by the array of storage cells 10, an additional memory 50, for example a non-volatile memory, intended to store the configuration data of the permutation circuit 30.
    Thus, in the example of FIG. 7, the configuration register 36 of the permutation circuit 30 is connected not to the input-output circuit 10 of the main memory as in the example of FIG. 3, but to a output port (not detailed in FIG. 7) of the additional memory 50.
    [0075]
    In the example of the figure to implement a permutation operation by means of circuit 30, the control circuit CTRL commands, the reading of an input datum in the main memory, the writing of this datum, via the input-output circuit 10 of the main memory, in the data input register 32 of the permutation circuit 30, the reading of configuration data in the additional memory 50, and the writing of this data in the configuration register 36 of the permutation circuit 30. The result of the permutation is provided on the output port 34 of the permutation circuit 30, and can be directly rewritten in the main memory by
    The intermediary of the input-output circuit 10 of the main memory, without passing through circuits external to the memory circuit.
    The additional memory 50 is for example a resistive memory, for example of the RRAM or ReRAM type, formed above a semiconductor substrate, for example in silicon, in and on which the main memory and the circuits are formed. computation 20 and permutation 30 of the memory circuit.
    B17236 - DD18432 FIG. 8 illustrates in more detail an example of embodiment of the additional memory 50 in the memory circuit of FIG. 7. In this example, we consider the case where the permutation circuit 30 is a circuit of the type described in relation to FIG. 4. The additional memory 50 is divided into 2 * log2 (K) -l MOD modules of p rows by K / 2 columns each, p being an integer less than or equal to K! corresponding to the number of permutations stored. Each of the 2 * log2 (K) -l MOD modules of p rows by K / 2 columns can include an output port of dimension K / 2, that is to say adapted to supply simultaneously, on K / 2 nodes of separate outputs, the K / 2 bits of a row of the module. Each of the 2 * log2 (K) -l MOD modules of p rows by K / 2 columns has its K / 2 output nodes connected respectively to the K / 2 configuration nodes c of the elementary permutation cells 40 of one of the 2 * log2 (K) -l rows of K / 2 cells 40 of the permutation network, it being understood that the configuration nodes c of the cells 40 of distinct rows of the permutation network are respectively connected to output nodes of distinct MOD modules of additional memory 50.
    In each MOD module of the additional memory 50, each of the p rows of the module stores a configuration of the corresponding row of the permutation circuit 30, corresponding to one of the K! possible configurations of the permutation circuit 30. A row selection circuit (not detailed in FIG. 8), pax 'example common to the 2 * log2 (K) -l MOD modules of the additional memory 50, can be provided to choose the desired configuration of the permutation circuit 30.
    Compared to the memory circuit of FIG. 1, an advantage of the embodiments described in relation to FIGS. 3 to 8 is that they allow switching operations to be carried out directly in the memory circuit,
    B17236 - DD18432 without having to pass the data to be swapped by external circuits and in particular by data buses external to the memory circuit. Many data processing methods using permutations can thus be implemented in whole or in part by such a memory circuit pax 'example data encryption methods, image processing methods, inference algorithms artificial neural networks, etc.
    By way of example, a memory circuit of the type described in relation to FIGS. 3 to 8 can be used to implement a type of data encryption method
    AES (English Advanced Encryption Standard advanced encryption standard). Indeed, the AES standard includes at
    less two stages of permutation . i on data, which can be stakes used by such a wax ’Uit memory.
    More particularly, the AES standard comprises a step called SubBytes, during which an input data item, in the form of a vector of several words of 8 bits each (or bytes), undergoes a series of several permutations successive, chosen from a set of several series of permutations, called Sbox. The different configurations of the permutation circuit 30, corresponding to the different permutation series or Sbox, can be stored in the memory circuit, in the main memory in the example of FIG. 3 or in the additional memory in the example of the FIG. 7.
    FIG. 9 is a block diagram schematically representing an example of implementation of the SubBytes step of the AES standard in a memory circuit of the type described above.
    The AES standard also includes a step called
    ShiftRows, during which the second, third and fourth rows of a 4x4 byte matrix are shifted
    B17236 - DD18432 circularly 1 byte, two bytes, and three bytes, respectively. To carry out this operation, the data of the input matrix are for example arranged in the form of a row vector of 16 bytes corresponding to a concatenation of the four rows of the matrix. This vector is applied at the input of the permutation circuit 30. The permutation circuit 30 is configured to provide an output vector of 16 bytes corresponding to a concatenation of the first row of the input matrix, of the second row of the matrix input array circularly offset by 1 byte, third row of the input array circularly offset by 2 bytes, and fourth row of the input array circularly offset by three bytes. The corresponding configuration of the permutation circuit 30 can be stored in the memory circuit, in the main memory in the example of FIG. 3, or in the additional memory in the example of FIG. 7.
    FIG. 10 schematically illustrates an example of implementation of the ShiftRows step of the AES standard in a memory circuit of the type described above.
    The measurements made by the applicant have shown that by using a memory circuit of the type described above, a gain of a factor of 12.4 in terms of execution time and a gain of a factor of 5, 6 in terms of electrical consumption can be obtained compared to. a conventional implementation, by means of a microprocessor, for example a processor of the Cortex M0 + type.
    As a variant, a memory circuit of the type described in relation to FIGS. 3 to 8 can be used to implement a method of image compression of the JPEG type.
    B17236 - DD18432 The JPEG compression algorithm notably includes a step of transforming colors from the RGB domain (red / green / blue) to the YUV domain (luminance / chrominance) For this, we carry out, for each pixel of l 'image, a multiplication of a vector of three values, corresponding respectively to the components R, G and B of the pixel, by a matrix of 3x3 predetermined coefficients. The result of this multiplication is a vector of three values, corresponding respectively to the components Y, U and V of the transformed image.
    Figure 11, part (A), schematically illustrates this operation. FIG. 11, part (B), illustrates an example of implementation of this operation by means of a memory circuit of the type described in relation to FIGS. 3 to 8.
    In the illustration of FIG. 11 (A), the three values R, G, B of the pixel define an input column vector, the values Y, U, V of the pixel define an output column vector, and the transformation matrix is a matrix of three rows by three columns, the coefficients of the first row of the matrix being called respectively pO, pl and p2, the coefficients of the second row of the matrix being called respectively p3, p4 and p5, and the coefficients of the third row of the matrix being called p6, p7 and p8 respectively.
    In the example of implementation of FIG. 11 (B), the values of the pixels of the image are stored in the form of a row vector L1 in memory. In FIG. 11 (B), row L1 of nine values R (l), R (3), G (3), B (3), corresponding G and B of a first pixel of 1 of a second pixel of the image, third pixel of the image.
    a first row of the circuit we represented a vector
    G (1), B (1), R (2), G (2), B (2), respectively to the values R, image, to the values R, G and B and to the values R, G and B of a
    B17236 - DD18432 The coefficients of the transformation matrix are stored in the form of a row vector L2 in a second row of the memory circuit. In FIG. 11 (B), a row vector L2 of nine values pO, pl, p2, p3, p4, p5, p6, p7, p8 is represented corresponding to a concatenation of the three rows of the transformation matrix.
    In addition, FIG. 11 (B) shows a row vector L3 of nine values, initially zero, stored in a third row of the memory circuit.
    In this example, the color transformation operation is entirely implemented within the memory circuit, in three cycles each comprising a multiplication and addition operation. At each cycle, the operation L3 = L1 * L2 + L3 is carried out. In other words, at each cycle, each of the values L3 (q) of the vector L3 is incremented by the value L1 (q) * L2 (q), where q is an integer ranging from 1 to 9 designating the position of the data in the vectors LI, L2 and L3. This multiplication and addition operation can be implemented by the calculation circuit 20 of the memory circuit. After each multiplication and addition operation and before the following multiplication and addition operation, the values of the row vector L2 are swapped so as to achieve a circular shift of three values (to the right in the orientation of FIG. 11) by the transformation coefficients. This operation can be implemented by the permutation circuit 30 of the memory circuit.
    Thus, in three cycles, the color transformation of three pixels of the image can be carried out. In practice, a much higher number of pixels can be processed simultaneously, by increasing the dimensions of the vectors L1, L2 and L3 and by repeating several times in the vector L2 the series of transformation coefficients pO, pl, p2, p3, p4 , p5, p6, p7 and p8. The three circuit configurations
    B17236 - DD18432 permutation necessary for the implementation of this step can be stored in the memory circuit, in the main memory in the example of FIG. 3, or in the additional memory in the example of FIG. 7. More generally , the implementation example described in relation to FIG. 11 (B) can be adapted to any application comprising one or more operations of multiplication of a matrix by a vector.
    The JPEG compression algorithm further includes a step of sub-sampling the image in YUV format. This step can be implemented by means of the permutation circuit 30. More particularly, the permutation circuit 30 can be used to reorder the data of a row of the memory containing the complete YUV representation of the image, so as to keep only part of the image, as defined by the JPEG standard. The corresponding configuration of the permutation circuit can be stored in the memory circuit, in the main memory in the example of FIG. 3 or in the additional memory in the example of FIG. 7.
    The JPEG compression algorithm further comprises a step of calculating a discrete cosine transform (DCT) of the sub-sampled YUV image. This step can be implemented entirely within the memory circuit, using the calculation circuit 20 and the permutation circuit 30.
    The JPEG compression algorithm further comprises a step of entropy coding of blocks of 8 * 8 values generated at the end of the step of calculating DCT. During this step, advantage can be taken of the permutation circuit 30 to reorder the blocks of 8 * 8 values from the DCT calculation step.
    [0098] Thus, all or most of the steps of a JPEG compression algorithm can be implemented directly
    B17236 - DD18432 within a memory circuit of the type described in relation to FIGS. 3 to 8, without having to pass data outside the memory circuit.
    Alternatively, a memory circuit of the type described in connection with Figures 3 to 8 can be used to implement an inference algorithm of an artificial neural network. Many artificial intelligence applications use artificial neural networks to make decisions on the input database. These applications are divided into two phases, a so-called learning phase, and a so-called inference phase. During the learning phase, the application learns to make a decision. For example, a large number of images, including images representing a cat and images not representing a cat, are presented. The images of cats are identified as such and the application calculates a set of values defining a network of artificial neurons making it possible to automatically identify a representative image of a cat. During the learning phase, large databases are used, and very large computational capacities are necessary. The inference phase consists in using the artificial neural network calculated during the learning phase to make a decision on the input database, for example to detect the possible presence of a cat on a picture. The inference phase is based on arithmetic operations and in particular multiplication of matrices, which can easily be implemented in a memory circuit of the type described in relation to FIGS. 3 to 8.
    We consider below, by way of example, a matrix multiplication operation R = A * B, where A and B are matrices of 4 rows by 4 columns defined as follows:
    [Math 1]
    B17236 - DD18432
    AT
    aOO a01 a02 a03 alO garlic al 2 al3 îi20 a21 a22 a23 _a30 a31 a32 a33
    and [Math 2]
    600 601 602 603 b 10 611 612 613 620 621 622 623 .630 631 632 633
    To implement the operation R = A * B by means of a memory circuit of the type described in relation to FIGS. 3 to 8, each of the matrices can be stored in a row of the memory, in the form of a corresponding row vector
    cl 13 concatenation of values of that our rows citB Here matric e. [0102] The BT transpose of the matrix B, defined as Follows: [Math 3] '600 610 620 630 ’ BT = 601 611 621 623 602 612 622 632 .603 613 623 633J can then be calculated in uti reading the circuit of.
    permutation 30 of the memory circuit.
    The row vectors containing the matrix A. and the rn.atr.ice BT can be multiplied point to point using the calculation circuit 20 of the memory circuit.
    The accumulations of the results of the by-products (a00 * b00, a01 * bl0, a02 * b20, a03 * b30, a! 0 * b01, all * bll, al2 * b21, al3 * b31, a2 0 * b02 , a21 * bl2, a22 * b22, a23 * b32, a30 * b03, a31 * bl3, a32 * b23, a33 * b33) to calculate the 4 * 4 coefficients of the matrix R can be performed iteratively by the circuit of calculation 20 of the memory circuit.
    [0105] Thus, all or most of the steps of an inference algorithm of an artificial neural network can be
    B17236 - DD18432 implemented directly within a memory circuit of the type described in relation to FIGS. 3 to 8, without having to pass data outside the memory circuit.
    By way of example, using a memory circuit of the type described above, two matrix multiplications can be carried out in 6 memory cycles. The number of operations is 32 per cycle and per matrix (16 additions and 16 multiplications), or 64 operations per cycle. In terms of data movement, it is advisable to provide a memory instruction for the rotation of the matrix, and four memory instructions for the implementation of the two matrix multiplications, that is to say 5 memory access versus 64 read access for a standard implementation via a microprocessor.
    More generally, the example of implementation of a matrix multiplication operation described above can be adapted to any application comprising one or more matrix multiplication operations.
    Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will appear to those skilled in the art. In particular, the embodiments described are not limited to the examples of application of the memory circuit mentioned in the present description. In addition, the embodiments described are not limited to the examples of implementation of the permutation circuit described in relation to FIGS. 4 to 6. In addition, the embodiments described are not limited to the particular example of cells elementary storage 10 described in relation to FIG. 2.
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. Memory circuit (200; 300) comprising:
    - a plurality of elementary storage cells (10) arranged in a matrix according to rows and columns, the cells of the same column sharing a same read bit line (RBL) and a same write bit line (WBL );
    an internal control circuit (CTRL ·) adapted to implement a calculation operation comprising the simultaneous activation in reading of at least two rows of the matrix; and
    - a permutation circuit (30) comprising a data input register (32), a configuration register (36) and an output port (34), the permutation circuit (30) being adapted to supply on its port output (34) the data stored in its input register (32) permuted according to a permutation defined as a function of the state of its configuration register (36).
    [2" id="c-fr-0002]
    2. Memory circuit (200; 300} according to claim 1, in which the internal control circuit (CTRL} is adapted to implement a permutation operation comprising:
    ~ activation in reading of at least a first row of the matrix;
    - copying data read from the read bit lines (RBL) of the matrix into the data input register (32) of the permutation circuit (30);
    - the copy of data supplied on the output port (34) of the permutation circuit (30) on the write bit lines (WBL) of the matrix; and ~ the write activation of at least one row of the matrix.
    B17236 - DD18432
    [3" id="c-fr-0003]
    3. Memory circuit (200) according to claim 2, in which the permutation operation further comprises:
    - the activation in reading of at least a second row of the matrix; and ~ copying data read from the read bit lines (RBL) of the matrix into the configuration register (36) of the permutation circuit (30).
    [4" id="c-fr-0004]
    4. Memory circuit (300) according to claim 1 or 2, comprising, in addition to the matrix of elementary storage cells (10), an additional memory (50) intended to store configuration data of the pe rmu tat ion circuit (30).
    [5" id="c-fr-0005]
    5. Memory circuit (300) according to claim 4 in its connection with claim 2, wherein the permutation operation further comprises copying data read from the additional memory (50) in the configuration register (36) of the permutation circuit (30).
    [6" id="c-fr-0006]
    6. Memory circuit (300) according to claim 4 or 5, wherein the additional memory (50) is a non-volatile memory.
    [7" id="c-fr-0007]
    7. Memory circuit (200; 300) according to any one of claims 1 to 6, in which the permutation circuit (30) comprises a plurality of elementary permutation cells (40) each comprising two data inputs el and e2, two data outputs si and s2, and a configuration input
    [8" id="c-fr-0008]
    8. Memory circuit (200; 300) according to claim 7, in which the permutation circuit comprises (K / 2) * (2 * log2 (K) 1) elementary permutation cells (40) arranged according to a Benes network, where K is an integer designating the
    B17236 - DD18432 dimension of the input register (32) and the output port (34) of the permutation circuit (30).
    [9" id="c-fr-0009]
    9. Memory circuit (200; 300) according to claim 7, in which the permutation circuit comprises 16 elementary permutation cells (40) arranged in 5 rows, the rows of rank 1 = 1 to 1 = 3 each comprising 4 elementary cells (40), and the rows of row 1 = 4 to 1 = 5 each comprising 2 elementary cells (40), the input register (32) and the output port (34) of the permutation circuit (30) being dimension 8, and 1 being an integer ranging from 1 to 5.
    Input-output memory circuit (
    [10" id="c-fr-0010]
    10) (200; 300) according to any one of claims 1 to 9, further including a configurable circuit for connecting the read bit lines (RBL) of the matrix to the input register (32) of the permutation circuit (30) and / or to connect the write bit lines output (34) of the circuit of (WBJLj) of the matrix to the permutation port (30).
    [11" id="c-fr-0011]
    11. Memory circuit (200; 300) according to claim 10, further comprising a calculation circuit (20) adapted to implement logical or arithmetic operations having as operands data stored in the matrix of elementary storage cells (10 ) of the memory circuit.
    [12" id="c-fr-0012]
    12. Memory circuit (200; 300) according to claim 11, in which the input-output circuit (10) is further configurable to connect the read bit lines (RBL) of the matrix to an input register. (22) of the calculation circuit (20) and / or for connecting the write bit lines (WBL) of the matrix to an output port (24) of the calculation circuit (20).
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    同族专利:
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    US11031076B2|2021-06-08|
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    US20200160905A1|2020-05-21|
    EP3660849A1|2020-06-03|
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    法律状态:
    2019-11-29| PLFP| Fee payment|Year of fee payment: 2 |
    2020-05-22| PLSC| Publication of the preliminary search report|Effective date: 20200522 |
    2020-11-30| PLFP| Fee payment|Year of fee payment: 3 |
    2021-11-30| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1871578A|FR3088767B1|2018-11-16|2018-11-16|MEMORY CIRCUIT SUITABLE FOR IMPLEMENTING CALCULATION OPERATIONS|FR1871578A| FR3088767B1|2018-11-16|2018-11-16|MEMORY CIRCUIT SUITABLE FOR IMPLEMENTING CALCULATION OPERATIONS|
    EP19209000.9A| EP3660849A1|2018-11-16|2019-11-13|Memory circuit suitable for performing computing operations|
    US16/684,987| US11031076B2|2018-11-16|2019-11-15|Memory circuit capable of implementing calculation operations|
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